/* $Header: iomap.h,v 2.2 01/10/02 10:30:26 przybyls Exp $ */

/***********************************************************************/
/* INCLUDE FILE NAME: iomap.h                                          */
/* ==================                                                  */
/*                                                                     */
/* Authors:      Lesley Freed                                          */
/*                                                                     */
/* COMMENT:  This is an include file which declares all of the         */
/*           hardware addresses and bit positions for Jack.            */
/*                                                                     */
/*                                                                     */
/***********************************************************************/

#ifndef IOMAP_H
#define IOMAP_H

/* #include <typedefs.h> */

/*****************************/
/*   IFDEFS                  */
/*****************************/


/*****************************/
/*   SYMBOLIC CONSTANTS      */
/*****************************/

/* Oven and Zone Hardware */

/* On Masks for power relay and valves control register: ZONES_OUT1 */

#define OVEN_CNTCR_ON           0x01    /* Mask on for main contactor        */
#define ZONE_PWR_ON             0x02    /* Mask on for small zone contactor  */

#define VALVE1_ON               0x08    /* Mask on for 24 V valve #1         */
#define VALVE2_ON               0x10    /* Mask on for 24 V valve #2         */
#define VALVE3_ON               0x20    /* Mask on for 24 V valve #3         */
#define VALVE4_ON               0x40    /* Mask on for 24 V valve #4         */

/* Off Masks for power relay and valves control register: ZONES_OUT1 */

#define OVEN_CNTCR_OFF          0xfe /* Mask to turn OVEN CONTACTOR OFF       */
#define ZONE_PWR_OFF            0xfd /* Mask to turn SMALL ZONE CNTCTR OFF    */
#define VALVE_PWR_OFF           0xfb    /* Mask off for 24 V valves contactor */
#define VALVE1_OFF              0xf7    /* Mask off for 24 V valve #1        */
#define VALVE2_OFF              0xef    /* Mask off for 24 V valve #2        */
#define VALVE3_OFF              0xdf    /* Mask off for 24 V valve #3        */
#define VALVE4_OFF              0xbf    /* Mask off for 24 V valve #4        */


/* On Masks for zone drive register: ZONES_OUT2 */

#define ALL_ZONES_ON            0xfe    /* Mask to turn on all zones       */
#define CRYO_ON_MASK            0x01    /* Mask to turn CRYO on            */
#define OVEN_ON_MASK            0x02    /* Mask to turn OVEN on            */
#define DETA_ON_MASK            0x04    /* Mask to turn DETA on            */
#define DETB_ON_MASK            0x08    /* Mask to turn DETB on            */
#define INJA_ON_MASK            0x10    /* Mask to turn INJA on            */
#define INJB_ON_MASK            0x20    /* Mask to turn INJB on            */
#define AUXA_ON_MASK            0x40    /* Mask to turn AUXA on            */
#define AUXB_ON_MASK            0x80    /* Mask to turn AUXB on            */

/* Off Masks for zone drive register: ZONES_OUT2 */

#define ALL_ZONES_OFF           0x00    /* Mask to turn off all zones       */
#define CRYO_OFF_MASK           0xfe    /* Mask to turn CRYO off            */
#define OVEN_OFF_MASK           0xfd    /* Mask to turn OVEN off            */
#define DETA_OFF_MASK           0xfb    /* Mask to turn DETA off            */
#define DETB_OFF_MASK           0xf7    /* Mask to turn DETB off            */
#define INJA_OFF_MASK           0xef    /* Mask to turn INJA off            */
#define INJB_OFF_MASK           0xdf    /* Mask to turn INJB off            */
#define AUXA_OFF_MASK           0xbf    /* Mask to turn AUXA off            */
#define AUXB_OFF_MASK           0x7f    /* Mask to turn AUXB off            */

/* Masks for BOARD_TYPE  */
#define IS_VT_BOARD             0x01    /* Mask for Vireo/Tiger bit         */
                                        /* bit0 = 0 if 60201 board (tiger   */
                                        /* or vireo),1 if old vireo bd.     */

/* On Masks for 24 V Valves, Relays and Double buffer enable : ZONES_OUT3 */

#define RELAY1_ON               0x01    /* Mask to turn Relay #1 ON         */
#define RELAY2_ON               0x02    /* Mask to turn Relay #2 ON         */

#define VLV24_1_ON              0x04    /* Mask to turn 24 V Valve #1 ON    */
#define VLV24_2_ON              0x08    /* Mask to turn 24 V Valve #2 ON    */

#define INLTA_CRYO_ON           0x10    /* Mask to turn Inlet Cryo A ON     */
#define INLTB_CRYO_ON           0x20    /* Mask to turn Inlet Cryo B ON     */

#define SPLIT_VLVA_ON           0x10    /* Mask to turn Split Valve A ON    */
#define SPLIT_VLVB_ON           0x20    /* Mask to turn Split Valve B ON    */

/* Off Masks for 24 V Valves, Relays and Double buffer enable : ZONES_OUT3  */

#define RELAY1_OFF              0xfe    /* Mask to turn Relay #1 OFF        */
#define RELAY2_OFF              0xfd    /* Mask to turn Relay #2 OFF        */

#define VLV24_1_OFF             0xfb    /* Mask to turn 24 V Valve #1 OFF   */
#define VLV24_2_OFF             0xf7    /* Mask to turn 24 V Valve #2 OFF   */

#define INLT_CRYO1_OFF          0xef    /* Mask to turn Inlet Cryo #1 OFF   */
#define INLT_CRYO2_OFF          0xdf    /* Mask to turn Inlet Cryo #1 OFF   */

#define SPLIT_VLVA_OFF          0xef    /* Mask to turn Split Valve A ON    */
#define SPLIT_VLVB_OFF          0xdf    /* Mask to turn Split Valve B ON    */

/* On Masks for Flap Motor Windings, Inlet Fan and Split Valves: ZONES_OUT4 */

#define FLAP_F0_ON              0x01    /* Mask to drive flap winding f0    */
#define FLAP_F1_ON              0x02    /* Mask to drive flap winding f1    */
#define FLAP_F2_ON              0x04    /* Mask to drive flap winding f2    */
#define FLAP_F3_ON              0x08    /* Mask to drive flap winding f3    */

#define INLT_FAN_ON             0x10    /* Mask to turn Inlet Fan Motor ON  */

#define ALS_POWER_ON            0x20    /* Mask to enable ALS power */
#define ALS_POWER_OFF           0xDF    /* Mask to disable ALS power */


#define ZONES_FAULT_CLEAR       0x40    /* Mask to Enable Double Buffer Reg.s */

/* Off Masks for Flap Motor Windings, Inlet Fan and Split Valves: ZONES_OUT4 */

#define ALL_FLAP_OFF            0xf0    /* Mask to clear all flap bits  */

#define FLAP_F0_OFF             0xfe    /* Mask to drive flap winding f0    */
#define FLAP_F1_OFF             0xfd    /* Mask to drive flap winding f1    */
#define FLAP_F2_OFF             0xfb    /* Mask to drive flap winding f2    */
#define FLAP_F3_OFF             0xf7    /* Mask to drive flap winding f3    */

#define INLT_FAN_OFF            0xef    /* Mask to turn Inlet Fan Motor ON  */

#define ZONES_FAULT_SET         0xbf    /* Mask to Disable Double Buffer Regs */

/* Bit Masks for Zones/Oven Configuration Register: ZONES_CONFIG1 */

#define VLV1_INST               0x04 /* Mask to test active high 24V Valve 1 */
#define VLV2_INST               0x08 /* Mask to test active high 24V Valve 2 */
#define VLV3_INST               0x10 /* Mask to test active high 24V Valve 3 */
#define VLV4_INST               0x20 /* Mask to test active high 24V Valve 4 */
#define ALL_VLV_MASK            0x3c /* Mask to read only the valve config   */

#define SPLIT_VLVA_INST         0x40 /* Mask to test active high Split Valve A*/
#define SPLIT_VLVB_INST         0x80 /* Mask to test active high Split Valve B*/

/* Bit Masks for heated zone configuration/fault register: ZONES_CONFIG2 */

#define  M_LT_70_WATTS          0x01 /* Set: wattage > 30                     */
#define  M_LT_150_WATTS         0x02 /* Set: wattage > 70                     */
#define  M_GT_150_WATTS         0x04 /* Set: wattage > 150                    */
#define  M_OVER_CURRENT         0x08 /* Set: output shorted                   */
#define  ALS_CURRENT_TRIP       0x10 /* Mask to test for Als overcurrent */
#define CO2_INST                0x20    /* Mask to test active low CO2 Valve */
#define N2_INST                 0x40    /* Mask to test active low N2 Valve  */
#define PNEU_BD_PRESENT         0x80    /* Pneumatics Board Present     */

/* LED Section Masks */

/* Off Masks for LED's #1 Out:  ROWS_LED1 */

#define ALL_LEDS1_OFF           0x0f    /* Mask to turn off all LED1   */
#define RUN_LED_OFF             0xef    /* Run LED                     */
#define FINAL_LED_OFF           0xdf    /* FINAL time LED              */
#define RAMP_LED_OFF            0xbf    /* Ramp LED                    */
#define INIT_LED_OFF            0x7f    /* INIT time LED               */

/* Off Masks for LED's #2 Out:  LED2 */

#define ALL_LEDS2_OFF           0x00    /* Mask to turn off all LED2   */
#define FRONT_MISER_LED_OFF     0xfe    /* Front Miser Mode LED        */
#define BACK_MISER_LED_OFF      0xfd    /* Back Miser Mode LED         */
#define DEVIATION_LED_OFF       0xfb    /* Run Deviation LED           */
#define CLOCK_TBL_LED_OFF       0xf7    /* Clock Tbl LED               */
#define REMOTE_LED_OFF          0xef    /* Remote LED                  */
#define NOT_RDY_LED_OFF         0xdf    /* NOT Ready LED               */
#define POST_RUN_LED_OFF        0xbf    /* Post Run LED                */
#define PREP_RUN_LED_OFF        0x7f    /* Prep Run LED                */

/* On Masks for LED's #1 Out:  ROWS_LED1 */

#define ALL_LEDS1_ON            0xf0    /* Mask to turn on all LED1    */
#define RUN_LED_ON              0x10    /* Run LED                     */
#define FINAL_LED_ON            0x20    /* FINAL time LED              */
#define RAMP_LED_ON             0x40    /* Ramp LED                    */
#define INIT_LED_ON             0x80    /* INIT time LED               */

/* On Masks for LED's #2 Out:  LED2 */

#define ALL_LEDS2_ON            0xff    /* Mask to turn on all LED2    */
#define FRONT_MISER_LED_ON      0x01    /* Front Miser Mode LED        */
#define BACK_MISER_LED_ON       0x02    /* Back Miser Mode LED         */
#define DEVIATION_LED_ON        0x04    /* Run Deviation LED           */
#define CLOCK_TBL_LED_ON        0x08    /* Clock Tbl LED               */
#define REMOTE_LED_ON           0x10    /* Remote LED                  */
#define NOT_RDY_LED_ON          0x20    /* NOT Ready LED               */
#define POST_RUN_LED_ON         0x40    /* Post Run LED                */
#define PREP_RUN_LED_ON         0x80    /* Prep Run LED                */

/* Masks for KEYBOARD */
#define OVEN_DOOR_OPEN_MASK     0x01    /* Mask to read the oven door  */
                                        /* bit: 1 = OPEN, 0 = CLOSED   */

/* On Masks for detector ON/OFF, pneumatics DSP load control: DISCRETE_OUT1 */

#define DETA_BD_ON              0x01    /* Turn on Detector A            */
#define DETB_BD_ON              0x02    /* Turn on Detector B            */
#define DETA_INPUT4_ON          0x04    /* DETA pin #A3 */
#define DETA_INPUT5_ON          0x08    /* DETA pin #A7 */
#define CPFA_BD_ON              0x08    /* Turn on CPF BRD A - Front     */
#define DETB_INPUT4_ON          0x10    /* DETB pin #A3 */
#define DETB_INPUT5_ON          0x20    /* DETB pin #A7 */
#define CPFB_BD_ON              0x20    /* Turn on CPF BRD B - Back      */

/* Off Masks for Detector ON/OFF Card Control: DISCRETE_OUT1 */

#define DETA_BD_OFF             0xfe    /* Turn off Detector A          */
#define DETB_BD_OFF             0xfd    /* Turn off Detector B          */
#define CPFA_BD_OFF             0xf7    /* Turn off CPF BRD A - Front     */
#define CPFB_BD_OFF             0xdf    /* Turn off CPF BRD B - Back      */

/* On Masks for Detector A/B Config: DISCRETE_OUT2 */

#define DETA_INPUT0_ON          0x01    /* DETA pin #C4 */
#define DETA_INPUT_DISABLE_ON   0x01

#define DETA_INPUT1_ON          0x02    /* DETA pin #B4 */
#define DETA_FID_IGNITOR_ON     0x02
#define DETA_FPD_IGNITOR_ON     0x02
#define DETA_ECD_N2_ON          0x02
#define DETA_NPD_BEAD_ON        0x02
#define DETA_TCD_VALVE_ON       0x02    /* only functions when input disabled */

#define DETA_INPUT2_ON          0x04    /* DETA pin #A4 */
#define DETA_TCD_N2_Ar_ON       0x04

#define DETA_INPUT3_ON          0x08    /* DETA pin #C3 */
#define DETA_TCD_HI_FILAMENT_TEMP_ON  0x08

#define DETB_INPUT0_ON          0x10    /* DETB pin #C4 */
#define DETB_INPUT_DISABLE_ON   0x10

#define DETB_INPUT1_ON          0x20    /* DETB pin #B4 */
#define DETB_FID_IGNITOR_ON     0x20
#define DETB_FPD_IGNITOR_ON     0x20
#define DETB_ECD_N2_ON          0x20
#define DETB_NPD_BEAD_ON        0x20
#define DETB_TCD_VALVE_ON       0x20    /* only functions when input disabled */

#define DETB_INPUT2_ON          0x40    /* DETB pin #A4 */
#define DETB_TCD_N2_Ar_ON       0x40

#define DETB_INPUT3_ON          0x80    /* DETB pin #C3 */
#define DETB_TCD_HI_FILAMENT_TEMP_ON  0x80

/* Off Masks for Detector A/B Config: DISCRETE_OUT2 */

#define DETA_INPUT0_OFF         0xfe    /* DETA pin #C4 */
#define DETA_INPUT_DISABLE_OFF  0xfe

#define DETA_INPUT1_OFF         0xfd    /* DETA pin #B4 */
#define DETA_FID_IGNITOR_OFF    0xfd
#define DETA_FPD_IGNITOR_OFF    0xfd
#define DETA_ECD_N2_OFF         0xfd
#define DETA_NPD_BEAD_OFF       0xfd
#define DETA_TCD_VALVE_OFF      0xfd    /* only functions when input disabled */

#define DETA_INPUT2_OFF         0xfb    /* DETA pin #A4 */
#define DETA_TCD_N2_Ar_OFF      0xfb

#define DETA_INPUT3_OFF         0xf7  /* DETA pin #C3 */
#define DETA_TCD_HI_FILAMENT_TEMP_OFF 0xf7

#define DETB_INPUT0_OFF         0xef    /* DETB pin #C4 */
#define DETB_INPUT_DISABLE_OFF  0xef

#define DETB_INPUT1_OFF         0xdf    /* DETB pin #B4 */
#define DETB_FID_IGNITOR_OFF    0xdf
#define DETB_FPD_IGNITOR_OFF    0xdf
#define DETB_ECD_N2_OFF         0xdf
#define DETB_NPD_BEAD_OFF       0xdf
#define DETB_TCD_VALVE_OFF      0xdf    /* only functions when input disabled */

#define DETB_INPUT2_OFF         0xbf    /* DETB pin #A4 */
#define DETB_TCD_N2_Ar_OFF      0xbf

#define DETB_INPUT3_OFF         0x7f    /* DETB pin #C3 */
#define DETB_TCD_HI_FILAMENT_TEMP_OFF 0x7f

/* Masks to control FPGA resets and readbacks */

#define RESET_MAIN_FPGA_MASK    0x08    /* Main FPGA on processor PORTE */
#define UNRESET_MAIN_FPGA_MASK  0xF7

#define TRIG_FPGA_LO            0xFE    /* FPGA readback trigger on PORTF */
#define TRIG_FPGA_HI            0x01

/* Masks to control the resets on RESET_LATCH1 */

#define RESET_PNEU_FPGA_MASK    0xFE    /* Pneumatic FPGA on RESET_LATCH1 */
#define UNRESET_PNEU_FPGA_MASK  0x01

#define PNEU_DSP_RMASK          0xFD    /* Mask to reset the Pneumatic DSP */
#define PNEU_DSP_UMASK          0x02    /* Mask to unreset the Pneumatic DSP */

#define UART_UMASK              0xEF    /* Mask to enable tray UART */
#define UART_RMASK              0x10    /* Mask to disable tray UART */

#define QUART_RMASK              0xFB    /* AND mask to reset QUART Chip */
#define QUART_UMASK              0x04    /* OR mask to unreset QUART Chip */

#define SIG_DSP_RMASK           0xF7    /* Mask to reset the Signal DSP */
#define SIG_DSP_UMASK           0x08    /* Mask to unreset the Signal DSP */


/*  Masks for BCD input */

#define BCD_MASK                0x0F    /* Isolate BCD after shifting */
#define BCD_VALID_MASK          0x1F    /* Isolate valid Vireo BCD    */


/*  Masks for beeper (EOS) */

#define BEEP_ON_MASK            0x01   /* OR mask for beeper on       */
#define BEEP_OFF_MASK           0x00   /* OR mask for beeper off      */
#define BEEP_1KHZ_MASK          0x02   /* OR mask to set 1KHz freq    */
#define BEEP_512_MASK           0x00   /* OR  mask to set 512 Hz freq */


/*  Masks for the Real Time Clock                       */

#define R_RTC_SECONDS           0x81   /* read address of RTC seconds   */
#define R_RTC_MINUTES           0x83   /* read address of RTC minutes   */
#define R_RTC_HOURS             0x85   /* read address of RTC hours     */
#define R_RTC_DAY               0x87   /* read addr of RTC day of month */
#define R_RTC_MONTH             0x89   /* read addr of RTC month        */
#define R_RTC_DAY_OF_WEEK       0x8B   /* read addr of RTC day (1 = Sunday */
#define R_RTC_YEAR              0x8D   /* read addr of RTC year         */
#define W_RTC_SECONDS           0x80   /* read address of RTC seconds   */
#define W_RTC_MINUTES           0x82   /* read address of RTC minutes   */
#define W_RTC_HOURS             0x84   /* read address of RTC hours     */
#define W_RTC_DAY               0x86   /* read addr of RTC day of month */
#define W_RTC_MONTH             0x88   /* read addr of RTC month        */
#define W_RTC_DAY_OF_WEEK       0x8A   /* read addr of RTC day (1 = Sunday */
#define W_RTC_YEAR              0x8C   /* read addr of RTC year         */
#define RTC_WR_CTRL             0x8E   /* addr & enable of W/R control reg */
#define RTC_ENABLE_WR           0x00   /* value for CTRL for writing    */
#define RTC_DISABLE_WR          0x80   /* value for CTRL for protect    */


/* Writable memory locations */

#define RAM     0x300000
#define RAM_END 0x3fffff


/* Read/Writable memory locations */

#define IO_MIN   0x400000
#define IO_MAX   0x4fffff

/* start of DRAM memory */
#define DMA_MEM   0x0312000
#define DRAM_MIN  DMA_MEM
#define DRAM_MAX  DMA_MEM+0xedbff

/*****************************/
/*   EXTERNALS               */
/*****************************/

/* Miscellaneous I/O */
/* See /src/iq/iomap/iomap.S for values assigned to below symbols */

        extern  volatile INT8   DSP_STATUS;     /* */
        extern  volatile INT8   DSP_BOOT;       /* */

        extern  volatile INT8   RESET_LATCH1;   /* */

        extern  volatile INT8   RT_CLOCK_ADDR;  /* Select internal register   */
                                                /* Address for Real Time Clk  */
                                                /* NOTE:  once you have writ- */
                                                /* ten to this you MUST do a  */
                                                /* subsequent read/write to   */
                                                /* deselect the register, i.e.*/
                                                /* RT_CLOCK_ADDR & RT_CLOCK_RW*/
                                                /* must be dealt w/ in pairs! */
        extern  volatile INT8   RT_CLOCK_R;     /* Real Time Clock Read  */
        extern  volatile INT8   RT_CLOCK_W;     /* Real Time Clock Write */

        extern  volatile INT8   MUX_ADC_WR;     /* 8-bit Muxed ADC channel    */
                                                /* select                     */
                                                /* NOTE:  writing to this     */
                                                /* starts an ADC conversion   */

        extern  volatile INT8   MUX_ADC_RDLO;   /* LS 8-bits of Muxed ADC rdg */
        extern  volatile INT8   MUX_ADC_RDMID;  /* Mid 8-bits of Muxed ADC rdg */
        extern  volatile INT8   MUX_ADC_RDHI;   /* MS 8-bits of Muxed ADC rdg */
        extern  volatile INT8   MUX_ADC_RDLO2;  /* LS 8-bits of 2nd Muxed ADC rdg */
        extern  volatile INT8   MUX_ADC_RDMID2; /* Mid 8-bits of 2nd Muxed ADC rdg */
        extern  volatile INT8   MUX_ADC_RDHI2;  /* MS 8-bits of 2nd Muxed ADC rdg */

        extern  volatile U_INT8 ATTN_ADDR;      /* output to Attn address & range*/
        extern  volatile U_INT8 ATTN_DATA;      /* output to Attn data        */

/* Discrete I/O */

        extern  volatile INT8   DISCRETE_IN1;   /* Detector Config:  Unique   */
                                                /* 4-bit code per detector    */
                                                /* type                       */

        extern  volatile INT8   DISCRETE_OUT1;  /* detector on/off            */
        extern  volatile INT8   DISCRETE_OUT2;  /* Detector A/B 4-bit general */
                                                /* purpose control            */

        extern  volatile INT8   APG_BUS_IN;     /* */
        extern  volatile INT8   APG_BUS_OUT;    /* */

        extern  volatile INT8   BOARD_TYPE;     /* New Vireo/Tiger vs. orig Vireo */

/* Thermal Zones I/O */

        extern  volatile INT8   ZONES_OUT1;     /* Triac Control, NOTE:      */
                                                /* writing to this address   */
                                                /* clears the Line Frequency */
                                                /* Interrupt                 */
        extern  volatile INT8   ZONES_OUT2;     /* */
        extern  volatile INT8   ZONES_OUT3;     /* */
        extern  volatile INT8   ZONES_OUT4;     /* */

        extern  volatile INT8   ZONES_CONFIG1;     /* cryo type, valve sense  */
        extern  volatile INT8   ZONES_CONFIG2;     /* zone config/fault reg   */
        extern  volatile INT8   ZONES_CONFIG2_CLR; /*clr zone config/fault reg*/

/* Display and Keyboard */

        extern  volatile INT8   DISPLAY;        /* Display Out */
        extern  volatile INT8   ROWS_LED1;      /* Rows Select and LEDS 1 Out */
        extern  volatile INT8   LED2;           /* LEDS 2 Out */
        extern  volatile INT8   KEYBOARD;       /* Keyboard In */
        extern  volatile INT8   BEEP_OUT;       /* beeper on/off, freq */

/* Multiport Valve */

        extern  volatile BIT8   BCD_IN;         /* BCD input, 2 digits */


/* DUART */

        extern  volatile BIT8   DUART;          /* */
        extern  volatile BIT8   DUARTA;         /* */
        extern  volatile BIT8   DUARTB;         /* */
        extern  volatile BIT8   DUARTC;         /* */
        extern  volatile BIT8   DUARTD;         /* */

/* UART */

        extern  volatile BIT8   UART;
        extern  volatile BIT8   UART_RHR;
        extern  volatile BIT8   UART_ISR;
        extern  volatile BIT8   UART_LSR;
        extern  volatile BIT8   UART_MSR;
        extern  volatile BIT8   UART_THR;
        extern  volatile BIT8   UART_IER;
        extern  volatile BIT8   UART_FCR;
        extern  volatile BIT8   UART_LCR;
        extern  volatile BIT8   UART_MCR;
        extern  volatile BIT8   UART_DLL;
        extern  volatile BIT8   UART_DLM;
        extern  volatile BIT8   UART_SPR;

/* INLET */

        extern  volatile BIT8   INLET_CTRL;     /* Inlet soleniod valve */

/*  SC26C92 READ/WRITE REGISTERS  */
      extern volatile BIT8  DUART_GCCR;       /* Global Config Ctrl Reg */
      extern volatile BIT8  DUART_WDTRCR;     /* Watch Dog Timer Run Control Reg */
      extern volatile BIT8  DUART_ICR;        /* Interrupt Control Register */
      extern volatile BIT8  DUART_MRA0;       /* Mode Reg */
      extern volatile BIT8  DUART_MRA1;       /* Mode Reg */
      extern volatile BIT8  DUART_MRA2;       /* Mode Reg */
      extern volatile BIT8  DUART_MRB0;       /* Mode Reg */
      extern volatile BIT8  DUART_MRB1;       /* Mode Reg */
      extern volatile BIT8  DUART_MRB2;       /* Mode Reg */
      extern volatile BIT8  DUART_MRC0;       /* Mode Reg */
      extern volatile BIT8  DUART_MRC1;       /* Mode Reg */
      extern volatile BIT8  DUART_MRC2;       /* Mode Reg */
      extern volatile BIT8  DUART_MRD0;       /* Mode Reg */
      extern volatile BIT8  DUART_MRD1;       /* Mode Reg */
      extern volatile BIT8  DUART_MRD2;       /* Mode Reg */
      extern volatile BIT8  DUART_CSRXRA;     /* Clock Select Reg */
      extern volatile BIT8  DUART_CSTXRA;     /* Clock Select Reg */
      extern volatile BIT8  DUART_CSRXRB;     /* Clock Select Reg */
      extern volatile BIT8  DUART_CSTXRB;     /* Clock Select Reg */
      extern volatile BIT8  DUART_CSRXRC;     /* Clock Select Reg */
      extern volatile BIT8  DUART_CSTXRC;     /* Clock Select Reg */
      extern volatile BIT8  DUART_CSRXRD;     /* Clock Select Reg */
      extern volatile BIT8  DUART_CSTXRD;     /* Clock Select Reg */
      extern volatile BIT8  DUART_IOPCRA;     /* I/O Port Config Reg */
      extern volatile BIT8  DUART_IOPCRB;     /* I/O Port Config Reg */
      extern volatile BIT8  DUART_IOPCRC;     /* I/O Port Config Reg */
      extern volatile BIT8  DUART_IOPCRD;     /* I/O Port Config Reg */
      extern volatile BIT8  DUART_GPOR;       /* GP I/O Port Reg */
      extern volatile BIT8  DUART_GPOCR;      /* GP I/O Port Clock Reg */
      extern volatile BIT8  DUART_GPODR;      /* GP I/O Port Data Reg */
      extern volatile BIT8  DUART_GPOSR;      /* GP I/O Port Select Reg */

/*  SC26C92 READ REGISTERS  */
      extern volatile BIT8  DUART_SRA;        /* Status Reg */
      extern volatile BIT8  DUART_RX_A;       /* Receive Reg */
/*    extern volatile BIT8  DUART_IPCR;    */ /* Input Port Change Reg */
      extern volatile BIT8  DUART_IStatRA;    /* Interrupt Status Reg */
      extern volatile BIT8  DUART_IStatRB;    /* Interrupt Status Reg */
      extern volatile BIT8  DUART_IStatRC;    /* Interrupt Status Reg */
      extern volatile BIT8  DUART_IStatRD;    /* Interrupt Status Reg */
/*    extern volatile BIT8  DUART_CTU;     */ /* Counter/Timer Upper Value */
/*    extern volatile BIT8  DUART_CTL;     */ /* Counter/Timer Lower Value */
      extern volatile BIT8  DUART_SRB;        /* Status Reg */
      extern volatile BIT8  DUART_SRC;        /* Status Reg */
      extern volatile BIT8  DUART_SRD;        /* Status Reg */
      extern volatile BIT8  DUART_RX_B;       /* Receive Reg */
      extern volatile BIT8  DUART_RX_C;       /* Receive Reg */
      extern volatile BIT8  DUART_RX_D;       /* Receive Reg */
      extern volatile BIT8  DUART_IPRA;       /* Input Port Reg */
      extern volatile BIT8  DUART_IPRB;       /* Input Port Reg */
      extern volatile BIT8  DUART_IPRC;       /* Input Port Reg */
      extern volatile BIT8  DUART_IPRD;       /* Input Port Reg */
      extern volatile BIT8  DUART_CIR;        /* Current Interrupt Reg */
/*    extern volatile BIT8  DUART_IPR;     */ /* Input Port Reg */
/*    extern volatile BIT8  DUART_START_CNTR;*/ /* Start Counter Cmd */
/*    extern volatile BIT8  DUART_STOP_CNTR; */ /* Stop Counter Cmd */

/*  SC26C92 WRITE REGISTERS  */
/*    extern volatile BIT8  DUART_CSRA;    */ /* Clock Select Reg */
      extern volatile BIT8  DUART_COMMON_CMD; /* Command Reg */
      extern volatile BIT8  DUART_CRA;        /* Command Reg */
      extern volatile BIT8  DUART_TX_A;       /* Transmit Reg */
/*    extern volatile BIT8  DUART_ACR;     */ /* Auxiliary Control Reg */
      extern volatile BIT8  DUART_IMRA;       /* Interrupt Mask Reg */
      extern volatile BIT8  DUART_IMRB;       /* Interrupt Mask Reg */
      extern volatile BIT8  DUART_IMRC;       /* Interrupt Mask Reg */
      extern volatile BIT8  DUART_IMRD;       /* Interrupt Mask Reg */
/*    extern volatile BIT8  DUART_CTPU;    */ /* C/T Upper Preset Reg */
/*    extern volatile BIT8  DUART_CTPL;    */ /* C/T lower Preset Reg */
/*    extern volatile BIT8  DUART_CSRB;    */ /* Clock Select Reg */
      extern volatile BIT8  DUART_CRB;        /* Command Reg */
      extern volatile BIT8  DUART_CRC;        /* Command Reg */
      extern volatile BIT8  DUART_CRD;        /* Command Reg */
      extern volatile BIT8  DUART_TX_B;       /* Transmit Reg */
/*    extern volatile BIT8  DUART_OPCR;    */ /* Output Port Conf Reg */
/*    extern volatile BIT8  DUART_SOPR;    */ /* Set Output Port Bits */
/*    extern volatile BIT8  DUART_ROPR;    */ /* Reset Output Port Bits */
      extern volatile BIT8  DUART_OPRA;       /* Output Port Reg */
      extern volatile BIT8  DUART_OPRB;       /* Output Port Reg */
      extern volatile BIT8  DUART_OPRC;       /* Output Port Reg */
      extern volatile BIT8  DUART_OPRD;       /* Output Port Reg */
      extern volatile BIT8  DUART_UCIR;       /* Update Current Interrupt Reg */

#endif
